The present invention relates to transistors and methods of manufacturing transistors.
Semiconductor devices become more powerful every year. One of the reasons why the power of the devices has steadily increased is that, every year, there are more and more transistors placed on a device. Concurrent with, and part of, the effort to place more transistors on a device is an effort to reduce the size of transistors. This effort also necessarily involves basic fabrication techniques of transistor structures.
There are many challenges being faced by those attempting to reduce transistor size. One method of reducing transistor size has been to reduce the size of the structures within a transistor. For example, gate lengths and junction depths have been steadily reduced. It has been found, however, that junction depth is important to the performance of the transistor. For example, the depth of the source and drain junctions of a transistor can be important in ensuring that a gate has enough control over the electron flow in the transistor. Further, junction depth can be important in the contact process for the source and drain terminals.
Generally, there are shallow and deep junctions in transition, and they have different depths. The shallow junction is useful to provide current flow between the source and drain in the transistor, and to achieve improved short channel effect. The deep junction is useful to improve the source and drain contact process.
Nevertheless, the shallow junction is one of the methods used in reducing the transistor size. Care should be taken in the fabrication of transistors to ensure that the junction depths in the transistor do not adversely affect the performance characteristics of the transistor.
Accordingly, new methods of manufacturing transistors to achieve smaller size are needed.
The present invention allows the manufacture of transistors having a shallow junction by using a two step epitaxial layer process. In accordance with a preferred embodiment, the fabrication process involves first depositing a spacer on a wafer and around gate structures, and then etching the spacer from the wafer. In the next step, a first silicon epitaxial layer is grown on the wafer. Then, a second spacer is deposited on the first silicon epitaxial layer and around the gate structures. Then the second spacer is etched from the first silicon epitaxial layer such that the second spacer remains around the gate structures. Next a second silicon epitaxial layer is grown on the first silicon epitaxial layer. Then, the second spacer is etched from around the gate structures. Then, ions are implanted at a first energy level to form four shallow junctions in areas near the gate structures. A third spacer is deposited on the second silicon epitaxial layer and around the gate structures, and then etched, such that the third spacer remains around the gate structures. Then, ions are implanted at a second energy level to form fifth and sixth junctions. The fifth junction is formed between the first and second inventors, and the sixth junction is formed between the third and fourth inventors.